CMOS image sensor array integrated circuits typically have at least two basic types of transistors, a P-type transistor having a P-doped poliysilicon gate, and an N-type transistor having an N-doped polysilicon gate. It is known that thresholds of N and P devices may be adjusted using an ion implant. CMOS image sensor array integrated circuits may have N and P type transistors with two or more threshold voltages determined by appropriately masked implants.
A common architecture for CMOS image sensor arrays uses a tiling unit within the sensor array. This tiling unit has at least one photodiode coupled to one or more transistors arranged to charge, or reset, an electrode of the photodiode to reverse-bias the photodiode to a known “reset” charge level. The photodiode is then exposed to a portion of a lit image, which may discharge some of the charge on the photodiode. The tiling unit also has a source follower coupled or coupleable to the photodiode and to a column sense line; the source follower serves as a buffer that allows reading of remaining charge on the photodiode.
In order to get good photodiode sensitivity, it is desirable to bias the photodiode to a high “reset” level. Black pixels, however, return nearly as high a voltage when read to the source follower as when charged. Should the reset charge level be near the power voltage to the source follower, and with a low threshold in the source-follower, this can give a low drop in the source-follower stage. With typical N-channel thresholds on the source follower, the follower has a low power-supply rejection ratio, potentially causing noise in pictures.